Specifications:

JEDEC Standard
Bandwidth(max): 5.3GB/s
Date Rate: 667MHz
Double Data Rate architecture
Differential Data Strobe (DQS)
Differential clock inputs (CK and /CK)
MRS cycle with address key programs

* CAS latency: 3, 4& 5* Burst length: 4 & 8* Burst type: Sequential & Interleave

2 variations of refresh

*Auto refresh & Self refresh

Edge aligned data output, center aligned data input
2 banks to be operated simultaneously or independently
Serial Presence Detect with EEPROM